Materials and Devices for End-Of-Roadmap and Beyond CMOS Scaling

This proceedings volume contains papers presented at Symposium I, 'Materials for End-of-Roadmap Scaling of CMOS Devices', and Symposium J, 'Materials and Devices for Beyond CMOS Scaling', held April 5–9 at the 2010 MRS Spring Meeting in San Francisco, California. These symposia attracted 106 presentations, of which twenty-two were invited. Historically, scaling in Si CMOS was primarily led by lithography. In the last decade, this situation has been completely revolutionized with the introduction of the likes of copper interconnects, high-k gate dielectrics, metal gates, and strained silicon to meet the demands of the International Technology Roadmap for Semiconductors as the technology generations were reduced beyond 45 nm. As we look towards the end of the roadmap and beyond, the proliferation of potential solutions to meet the necessary performance challenges becomes truly staggering, and has motivated an exponential increase in research in a wide range of emerging materials and devices architectures.